Hybrid Power Estimation for Telecommunication SoCs on Early Design Stages
Villota Coral, Jhonny Alexander (2021)
Villota Coral, Jhonny Alexander
2021
Master's Programme in Electrical Engineering
Informaatioteknologian ja viestinnän tiedekunta - Faculty of Information Technology and Communication Sciences
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Hyväksymispäivämäärä
2021-11-03
Julkaisun pysyvä osoite on
https://urn.fi/URN:NBN:fi:tuni-202110187688
https://urn.fi/URN:NBN:fi:tuni-202110187688
Tiivistelmä
Modern mobile networks require high-performance and low-power baseband processing systems. Those digital systems are designed as System-on-Chip (SoC), integrated circuits comprising billions of transistors into a single chip. The baseband processing SoCs are composed of several power-hungry engines such as the Layer-1 processing subsystem. That subsystem performs essential tasks for modern multicarrier and multiantenna techniques. Each task is executed in individual Intellectual Property (IP) blocks, independently developed, and progressively integrated into the subsystem. The most power-consuming functionalities of the subsystem are IFFT/FFT for OFDM symbol generation, decimation for the Physical Random-Access Channel (PRACH) signal extraction, sub-band filtering for mixed numerology carrier support, and Physical Resource Block (PRB) compression and decompression. The convergence of such high-computing processing tasks and multiple technologies into a single chip continuously increases the SoC power dissipation. Therefore, the power consumption is a crucial parameter on SoC design and must be estimated and tracked as early as possible in the design process to mitigate the problem through power optimizations. Nonetheless, the maturity of individual IP blocks at early design stages differs and generally does not include the final intended functionalities, which leads to inaccurate power estimates.
The main objective of this thesis is to simulate and model the power consumption of a Layer-1 subsystem which is part of a Digital Front-End (DFE) SoC. The subsystem is a high-performance 4G/5G baseband processing accelerator for Layer-1 in the 3GPP base station functional stack. The subsystem power estimation for different FDD/TDD test cases is calculated using individual IP power simulations in different modes of operation. The baseline IP power simulations were carried out at the Register-transfer level (RTL) and repeated at various design stages. In addition, gate-level simulations were also used in the latest design stage to calibrate the power model. The latest gate-level simulations have more design information; thus, they are considered the closest to the real results and are used to compare the early RTL power simulations and the power model.
In the worst case, using the first-round results of RTL simulations and without calibration, the power model produced a mean absolute error of 4.1% compared to the latest gate-level results. However, results also show that error decreases with calibration and as the design maturity progresses. In addition, a simple spreadsheet-like tool was developed to quickly estimate the subsystem power consumption for different test cases and processing capacities, allowing designers, integrators, and system architects to perform estimates without requiring new power simulations for each scenario. Finally, considering the concept of reuse of Intellectual Property (IP) blocks, the power database built serves as an accurate starting point for future similar projects.
The main objective of this thesis is to simulate and model the power consumption of a Layer-1 subsystem which is part of a Digital Front-End (DFE) SoC. The subsystem is a high-performance 4G/5G baseband processing accelerator for Layer-1 in the 3GPP base station functional stack. The subsystem power estimation for different FDD/TDD test cases is calculated using individual IP power simulations in different modes of operation. The baseline IP power simulations were carried out at the Register-transfer level (RTL) and repeated at various design stages. In addition, gate-level simulations were also used in the latest design stage to calibrate the power model. The latest gate-level simulations have more design information; thus, they are considered the closest to the real results and are used to compare the early RTL power simulations and the power model.
In the worst case, using the first-round results of RTL simulations and without calibration, the power model produced a mean absolute error of 4.1% compared to the latest gate-level results. However, results also show that error decreases with calibration and as the design maturity progresses. In addition, a simple spreadsheet-like tool was developed to quickly estimate the subsystem power consumption for different test cases and processing capacities, allowing designers, integrators, and system architects to perform estimates without requiring new power simulations for each scenario. Finally, considering the concept of reuse of Intellectual Property (IP) blocks, the power database built serves as an accurate starting point for future similar projects.