Signal Integrity Enhancements for Automated LPDDR4 Memory Testing System
Liikkanen, Petteri (2018)
Liikkanen, Petteri
2018
Sähkötekniikka
Tieto- ja sähkötekniikan tiedekunta - Faculty of Computing and Electrical Engineering
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Hyväksymispäivämäärä
2018-05-09
Julkaisun pysyvä osoite on
https://urn.fi/URN:NBN:fi:tty-201804241532
https://urn.fi/URN:NBN:fi:tty-201804241532
Tiivistelmä
Designing a smart phone requires plenty of testing, tweaking and verification to offer flawlessly functioning high-end products for the customers. Fine-tuning and verifying the memory interface between the application processor and memory, is one important area, which ensures the reliable operation of the device over different operating conditions. Automated testing process reduces the amount of manual measurements, and speeds up the development cycle of the product.
However, because of the rising bandwidth (BW) of memories, the signal integrity (SI) properties of the currently used memory testing system have begun to interfere with the device under test (DUT) by causing stability issues. Also, the measured waveforms have not been corresponding to the expected results with the latest memory modules with high data rates and clock speeds. This master’s thesis combines the previous experience and research about the topic, and introduces some new techniques to improve the measurement quality and to minimize the measurement system’s impact to signal properties of DUT.
The final goal is to upgrade the previously used automated memory testing system with newly developed techniques to allow good measurement quality with 4 th generation low power double data rate (LPDDR4) memories. In the future, the implemented system is meant to be compatible also with upcoming LPDDR memory generations, with very slight modifications.
With implemented memory testing system, there was no more previously mentioned stability issues and measured waveforms matched well to simulations. So at the end, the system performed as expected. There was couple of observations done during the designing and testing process which could improve the system marginally even further but they were not mandatory in terms of system’s operation, and could be implemented easily to next revisions of breakout printed wiring boards (PWB) for memories with different ball grid array (BGA) pinouts.
However, because of the rising bandwidth (BW) of memories, the signal integrity (SI) properties of the currently used memory testing system have begun to interfere with the device under test (DUT) by causing stability issues. Also, the measured waveforms have not been corresponding to the expected results with the latest memory modules with high data rates and clock speeds. This master’s thesis combines the previous experience and research about the topic, and introduces some new techniques to improve the measurement quality and to minimize the measurement system’s impact to signal properties of DUT.
The final goal is to upgrade the previously used automated memory testing system with newly developed techniques to allow good measurement quality with 4 th generation low power double data rate (LPDDR4) memories. In the future, the implemented system is meant to be compatible also with upcoming LPDDR memory generations, with very slight modifications.
With implemented memory testing system, there was no more previously mentioned stability issues and measured waveforms matched well to simulations. So at the end, the system performed as expected. There was couple of observations done during the designing and testing process which could improve the system marginally even further but they were not mandatory in terms of system’s operation, and could be implemented easily to next revisions of breakout printed wiring boards (PWB) for memories with different ball grid array (BGA) pinouts.