Design and Construction of A PLL System for A 96-MHz FM Transmitter

Abstract

The phase-locked loop (PLL) is used as frequency synthesizer in numerous electronic devices. This thesis presents design and construction of a basic PLL system on solderless breadboard, using discrete components and integrated circuits (ICs). The circuitry is designed to synthesize a 96-MHz sinusoidal signal, which can be used as the carrier wave for an FM transmitter. The circuitry includes a 24-MHz crystal oscillator (XO), a 96-MHz voltage-controlled oscillator (VCO), two frequency dividers, a phase detector (PD), and a loop filter (LF). In addition, a buffer amplifier is placed before each frequency divider for diminishing spurious frequencies. The XO provides 24-MHz reference frequency while the VCO is tunable between 86 MHz and 100 MHz. The constructed PLL system is able to lock the VCO frequency to 96 MHz. In this thesis, fundamental knowledge related to PLL is reviewed, and all building blocks of the PLL system are studied and analyzed. The challenges on utilizing IC chips are also discussed. Therefore this work provides a guide and reference for similar works and future study. For further research, the method of eliminating spurious frequencies and improving loop stability could be explored deeper to optimize the PLL performance.