Real-time FPGA implementation of nonlinear self-interference cancellation in full-duplex radio transceiver
Piililä, Mauno (2017)
2017
Tietotekniikka
Tieto- ja sähkötekniikan tiedekunta - Faculty of Computing and Electrical Engineering
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Hyväksymispäivämäärä
2017-12-07
Julkaisun pysyvä osoite on
https://urn.fi/URN:NBN:fi:tty-201710252060
https://urn.fi/URN:NBN:fi:tty-201710252060
Tiivistelmä
In full-duplex wireless communications, transmission and reception of signals occur simultaneously on the same center carrier frequency. It is one technique to increase limited wireless capacity, and particularly the spectral efficiency. The challenge of full-duplex tehnique is to separate the weak received signal from the transmitted signal, which can be even 120 dB stronger signal. This is called self-interference. Current duplexing techniques used in existing two-way communication systems are either time or frequency division duplexing, where signals received and transmitted utilizes different carrier frequencies, or transmission and reception are done in different time slots. The usage of full-duplex communications may, in theory, double the spectral efficiency of a wireless link and thereon the corresponding wireless system. To cancel the self-interference, and to recover the received signal, the self-interference has to be modelled accurately. Particularly important is the ability to model the nonlinear nature of the self-interference, that is caused by power amplifiers.
In this Master’s Thesis work, one recenty developed nonlinear self-interference model and corresponding nonlinear digital self-interference cancellation technique is explored. Specifically, a real-time FPGA implementation is pursued and developed for 20 MHz LTE-like channel bandwidth. This real-time Labview FPGA solution of digital self-interference canceller can, of the overall three-phase self-interference suppression solution, provide measured cancellation at maximum of about 34 dB. The other self-interference cancellation or isolation methods used in measurements are a passive circulator with 20 dB attenuation, and an active RF-canceller, that at measurements provided about 43 dB cancellation. Thus the total real-time cancellation of the self-interference in the overall demonstration system is maximally nearly 100 dB. The developed real-time FPGA implementation could possibly be used as a base for an ASIC circuit development. The resources available in the FPGA used, affected essentially into the structure of the canceller and to the performance of the cancellation.
In this Master’s Thesis work, one recenty developed nonlinear self-interference model and corresponding nonlinear digital self-interference cancellation technique is explored. Specifically, a real-time FPGA implementation is pursued and developed for 20 MHz LTE-like channel bandwidth. This real-time Labview FPGA solution of digital self-interference canceller can, of the overall three-phase self-interference suppression solution, provide measured cancellation at maximum of about 34 dB. The other self-interference cancellation or isolation methods used in measurements are a passive circulator with 20 dB attenuation, and an active RF-canceller, that at measurements provided about 43 dB cancellation. Thus the total real-time cancellation of the self-interference in the overall demonstration system is maximally nearly 100 dB. The developed real-time FPGA implementation could possibly be used as a base for an ASIC circuit development. The resources available in the FPGA used, affected essentially into the structure of the canceller and to the performance of the cancellation.