Programmable Inter-Device Block Transfer Hardware for Customized Heterogeneous Computing Platforms

Abstract

As requirements for performance and power efficiency grow more strict for high-performance computing and mobile devices, solutions are sought in customized processor architectures and heterogeneous computing platforms. However, these systems tend to be more complex than the homogeneous alternatives, and require more engineering effort to realize. In particular, utilizing the memory bus between the components in a heterogeneous system in a portable manner is not possible, as the various bus direct memory access cores are not designed for intercompatibility.

In this thesis, a specification for inter-device block transfer hardware interface is proposed. The specification is aimed for Heterogeneous Systems Architecture (HSA) and OpenCL platforms, allowing easy integration to existing systems. An application specific processor -based reference implementation is presented and evaluated on an FPGA-based video processing platform. The reference implementation reached a maximum bus utilization of 66 % on a Zynq- based SoC platform, and has been designed to be customizable for other platforms.