Image Processing Using Dataflow Techniques
Jingui, Li (2017)
2017
Information Technology
Tieto- ja sähkötekniikan tiedekunta - Faculty of Computing and Electrical Engineering
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Hyväksymispäivämäärä
2017-08-16
Julkaisun pysyvä osoite on
https://urn.fi/URN:NBN:fi:tty-201708241721
https://urn.fi/URN:NBN:fi:tty-201708241721
Tiivistelmä
Corner detection is an important task in digital image processing. Corner detection algorithms are widely used in pattern recognition, image mosaicing, motion detection, etc. The implementations of such algorithm in software/hardware can be challenging. One classical algorithm for finding corners in images is proposed by Harris and Stephens in 1988, commonly known as Harris corner detection algorithm; There have been different implementations of the algorithm in OpenCV and on FPGA. The implementations of the algorithm in hardware have been relatively less, and most importantly the architectures of the algorithm on FPGA have relatively been unexplored.
LIDE, created at University of Maryland, College Park, is a light-weight dataflow environment for rapid prototyping of DSP systems using dataflow techniques. The framework in C programming language is called LIDE-C, in Verilog HDL is called LIDE-V. This light-weight framework makes modeling of DSPs easy in both software and hardware. It is platform- and language-agnostic. This thesis work models the application both in LIDE-C and LIDE-V, our emphasis is, however, to propose multi-architecture corner detection Harris algorithm in LIDE-V. In LIDE, computations are distributed to different computation nodes in dataflow graphs. Each node is called actor in LIDE, and each actor has different modes of computation. Depending on how we construct a dataflow graph for an application and how we design actors of a dataflow graph, we easily create different implementations for the same algorithm.
In this thesis, different hardware architecture of the Harris algorithm will be proposed with different latency, resource usage, and throughput characteristics. Our preliminary results reveal, among other things, that unfolding for the non-max suppression actor not only improve performance but also decrease resource usage.
LIDE, created at University of Maryland, College Park, is a light-weight dataflow environment for rapid prototyping of DSP systems using dataflow techniques. The framework in C programming language is called LIDE-C, in Verilog HDL is called LIDE-V. This light-weight framework makes modeling of DSPs easy in both software and hardware. It is platform- and language-agnostic. This thesis work models the application both in LIDE-C and LIDE-V, our emphasis is, however, to propose multi-architecture corner detection Harris algorithm in LIDE-V. In LIDE, computations are distributed to different computation nodes in dataflow graphs. Each node is called actor in LIDE, and each actor has different modes of computation. Depending on how we construct a dataflow graph for an application and how we design actors of a dataflow graph, we easily create different implementations for the same algorithm.
In this thesis, different hardware architecture of the Harris algorithm will be proposed with different latency, resource usage, and throughput characteristics. Our preliminary results reveal, among other things, that unfolding for the non-max suppression actor not only improve performance but also decrease resource usage.