Hardware Prototyping with Matlab
Jalalinejad, Fatemeh (2017)
Jalalinejad, Fatemeh
2017
Electrical Engineering
Tieto- ja sähkötekniikan tiedekunta - Faculty of Computing and Electrical Engineering
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Hyväksymispäivämäärä
2017-04-05
Julkaisun pysyvä osoite on
https://urn.fi/URN:NBN:fi:tty-201703211194
https://urn.fi/URN:NBN:fi:tty-201703211194
Tiivistelmä
The goal of this thesis is to compare alternative ways to generate field programmable gate array (FPGA) implementations for signal processing systems defined in the Matlab environment using hardware description language (HDL) tools. As a case study, two-dimensional (2D) convolution is implemented with Mathworks Simulink Blocks and Matlab code. My challenge was mainly to create both Matlab and Simulink descriptions for 2D convolution, generate HDL code and compare the results. The Matlab code is written in such a way that that number of resources are optimized. To achieve this goal, some functions like transpose and for-loops are avoided. Writing an optimized code needs some experience.
At first, the FPGA design flow is described and then some basic elements of HDL Coder are explained. Then the HDL verifier including HDL cosimulation and FPGA-in-loop are described.
In FPGA design case study, 2D convolution is implemented with both Simulink and Matlab code. The code is optimized with techniques like mapping registers to RAM and resource sharing. With the help of resource sharing optimization, the number of multipli-ers decreased from 25 to 5 with the same functionality. However, the number of multi-plexers, adders/substractors and registers are increased somewhat.
In both Matlab and Simulink based implementations, timing optimizations are automati-cally activated, including methods like delay balancing, clock rate pipelining and dis-tributed pipelining. Therefore, in both implementations, the timing optimization is the same.
At first, the FPGA design flow is described and then some basic elements of HDL Coder are explained. Then the HDL verifier including HDL cosimulation and FPGA-in-loop are described.
In FPGA design case study, 2D convolution is implemented with both Simulink and Matlab code. The code is optimized with techniques like mapping registers to RAM and resource sharing. With the help of resource sharing optimization, the number of multipli-ers decreased from 25 to 5 with the same functionality. However, the number of multi-plexers, adders/substractors and registers are increased somewhat.
In both Matlab and Simulink based implementations, timing optimizations are automati-cally activated, including methods like delay balancing, clock rate pipelining and dis-tributed pipelining. Therefore, in both implementations, the timing optimization is the same.