Implementation of SystemVerilog and UVM Training

Abstract

Integrated circuits have become more complex every year and their verification has become more time-consuming. Therefore, effective education of new verification engineers is important for industry. This thesis covers planning of an efficient exercise package for education of verification engineers. The exercises cover key principles of SystemVerilog language and Universal Verification Methodology (UVM). The object of the exercise package is that a person with programming experience but no previous experience of system design or verification should be able to digest the most important concepts in five training days and be able to perform verification tasks using UVM after the training.

The planned exercise package was divided into four exercises on SystemVerilog language and seven exercises on UVM, which cover the methods the designer can use to aid in verification process and the basic principles of UVM methodology. The exercises were implemented as independent work so that the assistant was present to help solving problems and to answer questions. The planning of the exercises adapted to the needs of the participants on different levels so that every student was able to learn the most important concepts and additional more advanced tasks were provided for faster students. The advanced tasks did not introduce new crucial concepts, but deepened the understanding of the concepts used in the mandatory exercises.

The exercises were used as a part of digital design and verification education, where the participants had a programming background. The completion of learning objectives was metered by a time usage survey and a feedback form. Based on the results the learning objectives were fulfilled and every student was able to comprehend the concepts and the students were contented with the content and the structure of the exercises.