VCO start-up and stability analysis using time varying root locus
Sohail, Aneeb (2016)
2016
Master's Degree Programme in Electrical Engineering
Tieto- ja sähkötekniikan tiedekunta - Faculty of Computing and Electrical Engineering
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Hyväksymispäivämäärä
2016-05-04
Julkaisun pysyvä osoite on
https://urn.fi/URN:NBN:fi:tty-201604203837
https://urn.fi/URN:NBN:fi:tty-201604203837
Tiivistelmä
The oscillator circuit is one of the key components of the communication systems. It is necessary for an oscillator to provide the proper oscillations in order to confirm the stable operation of a communication circuit. There are many different analysis methods of analyzing the start-up and frequency stability of a system, but mostly it fails to analyze properly due to the parasitics involved. Somehow if any of them manages to compute the analysis it would be very complex, difficult and time consuming.
The time varying root locus (TVRL) approach can be utilized to analyze the start-up and frequency behavior of different oscillator designs. It is a theoretical based technique that can provide further insights into a circuit designer for oscillator operation. To analyze the start-up behavior, a semi-symbolic TVRL approach can be used with the help of the numerical QZ (Generalized Schur Decomposition) algorithm. By finding the time varying roots of polynomials, TVRL can help to estimate the undesired operating points. A symbolic TVRL analysis is capable of computing the system roots during an oscillation with the help of Muller algorithm.
Different numerical and the CAD (Computer Aided Design) tool are involved to implement this theoretical approach. Cadence 45nm CMOS General Process Design Kit (GPDK) helps to design the required schematic and SpectreRF simulator computes the time varying periodic solutions. Maple script can form an admittance matrix which is later used in MATALB to compute the final TVRL trajectories of dominant poles. The corresponding results are then analyzed to detect the failure mechanism which is responsible for relaxation oscillations.
In this thesis, an active inductor quadrature voltage controlled oscillator and five stage ring oscillator circuits are proposed to analyze thoroughly with the help of TVRL approach. The above mentioned techniques along with some extra computations have been implemented to verify whether the proposed circuits can overcome the relaxation oscillations and can produce the proper sinusoidal waveforms or there is a need to devise some modifications.
The time varying root locus (TVRL) approach can be utilized to analyze the start-up and frequency behavior of different oscillator designs. It is a theoretical based technique that can provide further insights into a circuit designer for oscillator operation. To analyze the start-up behavior, a semi-symbolic TVRL approach can be used with the help of the numerical QZ (Generalized Schur Decomposition) algorithm. By finding the time varying roots of polynomials, TVRL can help to estimate the undesired operating points. A symbolic TVRL analysis is capable of computing the system roots during an oscillation with the help of Muller algorithm.
Different numerical and the CAD (Computer Aided Design) tool are involved to implement this theoretical approach. Cadence 45nm CMOS General Process Design Kit (GPDK) helps to design the required schematic and SpectreRF simulator computes the time varying periodic solutions. Maple script can form an admittance matrix which is later used in MATALB to compute the final TVRL trajectories of dominant poles. The corresponding results are then analyzed to detect the failure mechanism which is responsible for relaxation oscillations.
In this thesis, an active inductor quadrature voltage controlled oscillator and five stage ring oscillator circuits are proposed to analyze thoroughly with the help of TVRL approach. The above mentioned techniques along with some extra computations have been implemented to verify whether the proposed circuits can overcome the relaxation oscillations and can produce the proper sinusoidal waveforms or there is a need to devise some modifications.