Implementation and Performance Analysis of Wishbone Shared Bus for Single Master-Multiple Slaves

Abstract

System on Chip interconnections are gaining importance as many IP cores are being integrated on a single chip and interconnect is the bottleneck for design speed. In this paper an asynchronous design comprised of single master and multiple slaves connected via point-to-point topology is analysed. This design resulted in large multiplexer, poor timing closure and consumed large interconnect area in FPGA. The aim of the thesis is to evaluate the system on-chip interconnections and implement the system with the synchronous shared bus interconnection. Many system-on-chip interconnections are reviewed in the thesis, which includes study of major types of buses from different vendors. Synchronous shared bus system is proposed as solution for the interconnections between single master and multiple slaves. Shared bus for the single master and multiple slaves is implemented using WISHBONE architecture and protocols for shared bus system. A general model is designed and implemented which is flexible to be tested for single master and any number of slaves. Performance evaluation is done for the design in terms of resource utilization and timings performance.