Design of A Flexible Timing Synchronization Scheme For Cognitive Radio Applications
Shamani, Farid (2013)
2013
Master's Degree Programme in Information Technology
Tieto- ja sähkötekniikan tiedekunta - Faculty of Computing and Electrical Engineering
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Hyväksymispäivämäärä
2013-12-04
Julkaisun pysyvä osoite on
https://urn.fi/URN:NBN:fi:tty-201312121483
https://urn.fi/URN:NBN:fi:tty-201312121483
Tiivistelmä
Advancements in wireless technology have increased different applications to demand higher data rate wireless access. Spectrum scarcity has come more into picture day by day. In this case, Cognitive Radios (CR)s are new emerged promising technology which are an alternative solution to use spectrum more efficiently. In concept, CR is defined as an intelligent wireless device which is always alerted about its environment by continuously sensing the spectrum as well as having the ability to dynamically adopt its radio parameters. Although, CRs can mitigate spectrum scarcity to some extent, a variety of challenges have emerged of which synchronization is one the most prominent.
This thesis first presents some of common synchronization techniques used in conventional receivers and, based on them, presents a flexible timing synchronization scheme in which the CR receivers are able to adopt their radio parameters with new information regarding to the spectrum.
The core content of the synchronizer is based on Finite Impulse Response (FIR) filter which performs as a multicorrelator on demand. To do so, different synchronization architectures have been applied to the design, including Multiplier-Less based correlator as well as Transposed, Sequential and Pipelined Direct Form FIR filters. Consequently, all the architectures are compared to each other in terms of power consumption, chip area, maximum frequency, etc. Compiled results show that the best strategy is to employ Multiplier-Less based multicorrelator as the fundamental functional unit of the synchronizer.
The aforementioned synchronization block is implemented on an Altera family FPGA board series Stratix-V. All the components are written in VHDL language and simulated through ModelSim software. Quartus-II version 12.1 environment is used to compile simulated codes.
This thesis first presents some of common synchronization techniques used in conventional receivers and, based on them, presents a flexible timing synchronization scheme in which the CR receivers are able to adopt their radio parameters with new information regarding to the spectrum.
The core content of the synchronizer is based on Finite Impulse Response (FIR) filter which performs as a multicorrelator on demand. To do so, different synchronization architectures have been applied to the design, including Multiplier-Less based correlator as well as Transposed, Sequential and Pipelined Direct Form FIR filters. Consequently, all the architectures are compared to each other in terms of power consumption, chip area, maximum frequency, etc. Compiled results show that the best strategy is to employ Multiplier-Less based multicorrelator as the fundamental functional unit of the synchronizer.
The aforementioned synchronization block is implemented on an Altera family FPGA board series Stratix-V. All the components are written in VHDL language and simulated through ModelSim software. Quartus-II version 12.1 environment is used to compile simulated codes.