A Security Architecture for a Wireless Memory
Aghababaee Tafreshi, Mona (2013)
2013
Master's Degree Programme in Information Technology
Tieto- ja sähkötekniikan tiedekunta - Faculty of Computing and Electrical Engineering
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Hyväksymispäivämäärä
2013-10-09
Julkaisun pysyvä osoite on
https://urn.fi/URN:NBN:fi:tty-201310241380
https://urn.fi/URN:NBN:fi:tty-201310241380
Tiivistelmä
Wireless memories are the new trend in memory technology and a result of the latest advances in wireless and data transfer technologies. Allowing transfer of large amounts of data between a host device (e.g., a computer, a mobile phone) and a battery-free wireless memory is essentially the goal of these devices. The advent of this class of memories has opened up the door to a wide range of applications for storing and sharing contents in a wireless manner. Most of the applications of a wireless memory system require a secure transfer of the data between the two sides. In this thesis, means to provide the required security for the wireless memory system is studied, implemented and demonstrated.
This thesis first studies some of the common security threats and the corresponding mechanisms to protect the communication of sensitive data from these threats. Additionally, it analyses some of the threats that are most probable in case of the communication between a wireless memory tag and a host device. Then, the security architecture implemented on the wireless memory’s tag side to secure the tag’s life-cycle is reviewed. This architecture is implemented based on the limited processing power available in the memory which is due to the fact that the memory tag is wirelessly powered by the host. It is also assumed that more complex mechanisms should be employed in the host side of the system.
The introduced security architecture was implemented using a Cyclone II FPGA board and the employed mechanisms were tested using a Linux machine as the host device. The implemented mechanisms guarantee confidentiality and integrity of the wireless channel between the two side of the communication as well as authentication, access control and secure life-cycle management of the wireless memory.
The number of clock cycles that different security operations need to be performed and the size of the security software were measured using the prototype hardware and synthesis tools con rm the feasibility of the implementation on the actual memory tag. In the future, when more processing capabilities are available on the memory tag, the wireless memory features may be expanded.
This thesis first studies some of the common security threats and the corresponding mechanisms to protect the communication of sensitive data from these threats. Additionally, it analyses some of the threats that are most probable in case of the communication between a wireless memory tag and a host device. Then, the security architecture implemented on the wireless memory’s tag side to secure the tag’s life-cycle is reviewed. This architecture is implemented based on the limited processing power available in the memory which is due to the fact that the memory tag is wirelessly powered by the host. It is also assumed that more complex mechanisms should be employed in the host side of the system.
The introduced security architecture was implemented using a Cyclone II FPGA board and the employed mechanisms were tested using a Linux machine as the host device. The implemented mechanisms guarantee confidentiality and integrity of the wireless channel between the two side of the communication as well as authentication, access control and secure life-cycle management of the wireless memory.
The number of clock cycles that different security operations need to be performed and the size of the security software were measured using the prototype hardware and synthesis tools con rm the feasibility of the implementation on the actual memory tag. In the future, when more processing capabilities are available on the memory tag, the wireless memory features may be expanded.