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Designing Exercise Work for System-on-Chip Course

Sadeharju, Jukka (2012)

 
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Sadeharju, Jukka
2012

Sähkötekniikan koulutusohjelma
Tieto- ja sähkötekniikan tiedekunta - Faculty of Computing and Electrical Engineering
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Hyväksymispäivämäärä
2012-08-15
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Julkaisun pysyvä osoite on
https://urn.fi/URN:NBN:fi:tty-201208311263
Tiivistelmä
Multiprocessor systems have become very popular system design during last decades.That is consequence of need for more and more efficient systems with low physical space. This kind of systems need several different system and design methods to give efficient system design and reasonable production expenses.

In this thesis I consider the contents and structure of the exercise work of the course “TKT-3541 SoC Platforms”. The purpose of the project is creating the exercise work that improves from the former exercise work of the same course. Different techniques and approaches are considered to give the best solutions for the work with certain time limitations.

This work tries to find the topics and content that fulfils the requirements which are set to it by the department of the computer sciences. Among general requirements for the course, the system of the exercise work tries to describe the real life systems-on-chip.

This work describes the phases and content of the exercise work. That exercise work teaches the principal structure of multiprocessor systems-on-chip and different approaches related to those systems. The exercise work is implemented to the field programmable gate array logic which makes possible to create different platform structures without physical changes.

The improvements to the former exercise work were numerous. Different parts of the platforms are more visible in new exercise work and design approaches used were clearer. For example, reuse is significant approach that is used better in the new exercise work. Also the abstractions and the interfaces are examples of the major improvements of the work.
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