Design of a Reconfigurable Multi-Core Architecture for Streaming Applications
Ghazanfari, Leyla S. (2012)
2012
Master's Degree Programme in Information Technology
Tieto- ja sähkötekniikan tiedekunta - Faculty of Computing and Electrical Engineering
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Hyväksymispäivämäärä
2012-06-06
Julkaisun pysyvä osoite on
https://urn.fi/URN:NBN:fi:tty-201206181199
https://urn.fi/URN:NBN:fi:tty-201206181199
Tiivistelmä
This thesis presents design of a reconfigurable multi-processor architecture.The architecture is composed of 9 nodes interconnected to each other through a 3x3 mesh-based Network-on-Chip. The central node of the architecture hosts a RISC processor. This node acts as master of the platform, taking care of the data and task scheduling. The surrounding nodes host a reconfigurable engine and do the actual processing.
The system was prototyped on an Altera FPGA device and RTL simulations of the architecture were carried out to ensure the correct functionality of the system. The platform was designed to process streaming applications. As an example of these applications, a finite impulse response filter was mapped on the system. Simulation results showed a speed-up of 6.8x over the same FIR filter implemented on a COFFEE RISC core, while requiring a 20% less resources of similar architecture composed by a homogeneous mesh of COFFEE RISC cores.
The system was prototyped on an Altera FPGA device and RTL simulations of the architecture were carried out to ensure the correct functionality of the system. The platform was designed to process streaming applications. As an example of these applications, a finite impulse response filter was mapped on the system. Simulation results showed a speed-up of 6.8x over the same FIR filter implemented on a COFFEE RISC core, while requiring a 20% less resources of similar architecture composed by a homogeneous mesh of COFFEE RISC cores.