ASIP Integration and Verification Flow

Abstract

Over the years, user-programmable logic devices, such as FPGAs, have become a popular platform for testing and implementing hardware designs. Intellectual Property (IP) components and synthesizable processor cores allow complex design to be implemented in a reasonable time, thanks to design reuse and the flexibility provided by programmability. Unfortunately, the performance of General Purpose Processors (GPP) is often inadequate, and creating custom fixed function hardware implementations to boost the performance is often too time consuming and expensive. Application-Specific Instruction-set Processors (ASIP) are one solution to match the performance of a custom fixed function hardware design and the flexibility of software by tailoring the processor architecture to match the specific application. In order to decrease the design time, and, thus, increase the productivity, a practical processor design environment is needed. TTA-based Co-design Environment (TCE), developed at Tampere University of Technology, allows the designer to tailor ASIPs based on the Transport Triggered Architecture (TTA) processor template and to generate ASIP implementations. However, previously the TTA ASIPs had to be manually integrated into the target platform, which restrains the otherwise fluent design flow. For this thesis, an automatic integration framework called Platform Integrator was created for TCE. The purpose of the framework is to automate the integration flow of TTA ASIPs to various FPGA platforms in order to reduce the design time. The design, implementation and verification of the Platform Integrator framework and three distinct Platform Integrator implementations are described in the thesis. Another part of this thesis documents the verification flow of TTA ASIPs. The thesis introduces a new verification tool called TTA Unit Tester which is designed and implemented to complete the verification flow. The purpose of the TTA Unit Tester is to automatically verify the processor datapath resources. The different steps of the verification flow are utilized to verify the ASIP implementations created with the Platform Integrators. /Kir11