Tools and Methodologies for Custom RISC-V Processors

Abstract

Modern computing systems are highly heterogeneous with multiple subsystems optimized for different computational use cases. Custom processors are widely adopted for accelerating application- and domain-specific workloads, without compromising compiler programmability. Despite the higher flexibility of programmable processors, designing, programming, and optimizing them is time-consuming and requires deep expertise. At the same time, interest in the open-standard RISC-V architecture has grown both in academia and industry. In recent years, RISC-V has been widely adopted in general-purpose processors with less attention having been paid to its potential in application- specific use cases, even though the instruction set is designed to be extensible. As such, research on combining RISC-V with static multi-issue execution has been limited.

To address these research gaps, this thesis proposes tools and methodologies for custom RISC-V processors. The proposed toolset integrates a unified architecture description that is used to automatically retarget the compiler and hardware generation tools for RISC-V application-specific instruction-set processors. As a result, custom RISC-V processors can be programmed using a high-level programming language and a matching synthesizable hardware description can be generated. As a means of introducing static multi-issue capabilities to the RISC-V instruction set architecture, a novel multi-instruction-set methodology combining an exposed datapath architecture with RISC-V is proposed. The complexity of optimizing the large design space of the exposed datapath template with a compiler-in-the-loop design cycle is mitigated by proposing a surrogate-assisted optimization framework. To demonstrate the real-world applicability of the tools and methodologies, this thesis presents a 22-nm tape-out of a custom digital signal processor that was designed and programmed using the proposed toolset.