A 1.2-3.4 Gb/s Low-Power Multiphase CDR with Glitch-Free Bang-Bang Phase Detector

Abstract

This paper presents a multiphase clock and data recovery (CDR) circuit for high-speed (1.2-3.4 Gb/s) display driver ICs (DDIs) with a novel glitch-free bang-bang phase detector (BBPD). Compared to conventional BBPDs, which often suffer from sampling glitches caused by latch-delay mismatches and asynchronous data-edge interferences, the proposed BBPD employs a robust sampling network ensuring mutually exclusive data-edge valid events, thereby filtering invalid transitions and minimizing timing-induced jitter. An extensive comparison with conventional BBPDs highlights these improvements and clarifies how the proposed BBPD enhances phase detection integrity and overall stability in high-speed CDRs. Fabricated in a 0.18-μm CMOS process and integrated in a chip-on-film (COF) package along with other DDI's components, the proposed CDR demonstrates a clean output phase trajectory and an improved 97 ps output jitter (0.388 UI at 4 Gb/s) with only 20.1 mW power consumption including the equalizer power. The overall CDR performance is also validated through a comprehensive characterization using a shmoo plot across 1.4 V - 2.2 V supply voltages.