SoC power-up reliability and verification improvement using a centralised power controller

Abstract

A reliable chip power-up sequence is one of the critical processes in chip design. As modern chips integrate increasingly diverse analog and digital subsystems with advanced power management techniques, verifying the correctness of the chip startup sequence at the design stage has become more challenging. As power-up is a cross-domain process spanning both the digital and analog domains, verification of the power-up sequence has become complicated. Failure to verify the startup sequence during the design stage can result in chip malfunction or unreliable operations. This thesis case study addresses the problem by proposing a centralised startup management Intellectual Property (IP) architecture, in which all startup sequencing and reset control logic is consolidated into a dedicated Finite State Machine (FSM) within the System-on-Chip's power management subsystem. The proposed startup management IP integrates both analog and digital macros and, after successful cold boot, it generates the reset to the digital domain. The FSM implements the startup sequence and provides control and status signals to the analog macros. The implemented design was verified in the company’s design environment. This thesis shows the advantages of having a centralised startup management IP to control startup sequence and reset behaviours in the System-on-Chip’s power management unit. The proposed approach enhances the correlation between analog and digital domain behaviours during critical power-up process and reset scenarios while improving reliability and reducing verification complexity. Furthermore, the architecture enables the reduction of certain analog macros by absorbing their sequencing responsibilities into the digital FSM, yielding benefits in verification and design maintainability. These findings show that centralising startup control into a well-structured IP offers a more robust and verifiable solution. This approach improves the reliability of power-up sequences in complex mixed-signal low-power System-on-Chip (SoC) designs.