Enhancing Functional Verification Accuracy and Efficiency Using LLMs

Abstract

The complexity of modern Integrated Circuit (IC) designs has significantly increased the effort required for functional verification and maintaining consistency across design components. Manual review of specifications, Register Transfer Level (RTL) implementations, and verification plans is time consuming and prone to human error, often resulting inconsistencies and incomplete verification coverage. This thesis presents an AI assisted framework developed in collaboration with Bosch Sensortec GmbH for automated consistency checking and verification coverage analysis and deployed for internal use within the organization. The framework integrates multiple AI driven workflows, including guideline-based specification review, structured RTL summarization, specification to RTL comparison, and verification plan analysis. Experimental results on real project designs from Bosch Sensortec, demonstrate reduced manual effort and improved accuracy in detecting mismatches and coverage gaps, high-lighting the effectiveness of AI assisted approaches in enhancing verification workflows.