Optimizing performance of fully embedded HEVC video encoder on FPGA
Nymark, Niklas (2026)
2026
Tietotekniikan DI-ohjelma - Master's Programme in Information Technology
Informaatioteknologian ja viestinnän tiedekunta - Faculty of Information Technology and Communication Sciences
Hyväksymispäivämäärä
2026-06-01
Julkaisun pysyvä osoite on
https://urn.fi/URN:NBN:fi:tuni-202605296595
https://urn.fi/URN:NBN:fi:tuni-202605296595
Tiivistelmä
Video content has increasingly become the number one source of internet traffic, with short-form content providers like TikTok and Instagram Reels exploding in popularity in recent years. Video capabilities are also getting more common in other fields, such as robotics, with drones and self-driving cars often requiring video input to be aware of their surroundings. These factors, along with the increasing image fidelity in newer handheld devices and personal computers has led to a growing need for efficient video coding methods for high-resolution video content.
One such video coding standard is High-Efficiency Video Coding (HEVC), which has slowly but surely become one of the most popular video encoding formats in the industry. HEVC is able to drastically reduce the size of a video while preserving excellent visual clarity. The cost to this is high computational complexity in the encoding process. With increasingly small devices like smartphones needing to capture and present high-resolution video in real time with strict power consumption limitations, hardware (HW) accelerated video coding becomes compulsory.
In this thesis, a real-time HEVC encoder is fully synthesized on a Field-Programmable Gate Array (FPGA), being able to independently compress high-definition video input without any help from an external Central Processing Unit (CPU). The proposed system synthesizes Nios II softcore processors on an FPGA to run Kvazaar, an open-source HEVC encoder software, while also using a HW intra prediction accelerator to boost performance. The proposed system is optimized for real-time video encoding with the inclusion of data caches, instruction caches and Direct Memory Access (DMA) units in order to maximize performance. A proof-of-concept, fully open-source version of the embedded video encoder is also presented, which uses open-source VexRiscV softcores to run Kvazaar. The video encoder presented in this thesis is able to achieve 25x higher performance after optimizations compared to a proof-of-concept version, which is possible thanks to the use of caches, DMAs and maximal clock frequencies.
One such video coding standard is High-Efficiency Video Coding (HEVC), which has slowly but surely become one of the most popular video encoding formats in the industry. HEVC is able to drastically reduce the size of a video while preserving excellent visual clarity. The cost to this is high computational complexity in the encoding process. With increasingly small devices like smartphones needing to capture and present high-resolution video in real time with strict power consumption limitations, hardware (HW) accelerated video coding becomes compulsory.
In this thesis, a real-time HEVC encoder is fully synthesized on a Field-Programmable Gate Array (FPGA), being able to independently compress high-definition video input without any help from an external Central Processing Unit (CPU). The proposed system synthesizes Nios II softcore processors on an FPGA to run Kvazaar, an open-source HEVC encoder software, while also using a HW intra prediction accelerator to boost performance. The proposed system is optimized for real-time video encoding with the inclusion of data caches, instruction caches and Direct Memory Access (DMA) units in order to maximize performance. A proof-of-concept, fully open-source version of the embedded video encoder is also presented, which uses open-source VexRiscV softcores to run Kvazaar. The video encoder presented in this thesis is able to achieve 25x higher performance after optimizations compared to a proof-of-concept version, which is possible thanks to the use of caches, DMAs and maximal clock frequencies.