Toward Capacitive In‐Memory‐Computing: A Device to Systems Level Perspective on the Future of Artificial Intelligence Hardware

Abstract

The quest for energy-efficient, scalable neuromorphic computing has elevated compute-in-memory (CIM) architectures to the forefront of hardware innovation. While memristive memories, such as resistive random-access memories, phase-change memory, magneto resistive random-access memory, and ferroelectric random-access memories, have been extensively explored for synaptic implementation in CIM architectures, their inherent limitations, including static power dissipation, sneak-path currents, and interconnect voltage drops, pose significant challenges for large-scale deployment, particularly at advanced technology nodes. In contrast, capacitive memories offer a compelling alternative by enabling charge-domain computation with virtually zero static power loss, intrinsic immunity to sneak paths, and simplified selector-less crossbar operation, while offering superior compatibility with 3D back-end-of-line integration. This perspective highlights the architectural and device-level advantages of emerging nonvolatile capacitive synapses, including metal–ferroelectric–metal, metal–ferroelectric–semiconductor, ferroelectric field-effect transistors, and hybrid configurations. We examine how material engineering and interface control can modulate synaptic behavior, capacitive memory window, and multilevel analog storage potential. Furthermore, we explore critical system-level trade-offs involving device-to-device variation, charge transfer noise, dynamic range, and effective analog resolution. Capacitive memories, we argue with custom-built stacks, have the potential to become a foundational technology for the next generation of extremely energy-efficient neuromorphic computing platforms.