Towards Predictable Ultra-Low Latency End-Nodes with Hardware-Accelerated Abstract Timers

Abstract

Distributed real-time systems require end-nodes with predictable and explicitly controllable timing characteristics. Abstract timers are a promising utility to improve the realtime capability of these resource-constrained embedded systems. However, the current implementations is based on critical section access to a software priority queue, which is detrimental to the latency and time-predictability of a given system. This work explores the use of a hardware-accelerated priority queue to significantly reduce the scheduling overhead of abstract timers. A novel microarchitecture for a hardware priority queue is proposed and improves on prior work by supporting all operations, including overflow detection, with no internal latency. The proposed design is evaluated against the legacy design with application-specific integrated circuit (ASIC) synthesis targeting a 22 nm TSMC technology node. The novel microarchitecture occupies between 18 % and 25 % of the legacy design area and does not contribute to the critical path when integrated to a full microcontroller platform. A functional evaluation against software-based abstract timers demonstrates how hardware priority queues can eliminate jitter while significantly lowering the overall element access latency and program memory footprint. A proposed virtualization scheme for timer queues demonstrates how even a small hardware instance can be used to improve the real-time performance of a system.