Resource Efficient Direct Digital Frequency Synthesizer Architecture on FPGA

Abstract

Direct Digital Frequency Synthesizer (DDFS) is a device that creates digital samples of analog signals. The DDFS designs commonly use memory to store these samples. However, as the accuracy increases, the size of the memory grows both in width and depth. In this paper, we present a resource efficient, 12-bit quadrature Direct Digital Frequency Synthesizer (DDFS) architecture that applies Taylor series approximation in the amplitude computation. The design is implemented on a field programmable gate array (FPGA), where it consumes 266 LUTs and 236 Flip-Flops. The design has high signal quality, and it reaches the spurious free dynamic range (SFDR) of -80.8 dBc.