Memory-Less 12-Bit Direct Digital Frequency Synthesizer Architecture on FPGA

Abstract

Direct digital frequency synthesizer (DDFS) is used to generate digital sinusoidal signals. Typically, the architectures utilize memory. However, in many applications, such as low cost FPGAs, the memory resources are scarce. In this paper, we present a memory-free, quadrature DDFS architecture. The memory-free operation is obtained by utilizing Chebyshev polynomial approximation in the amplitude computation. Additionally, both phase and amplitude dithering are applied to improve the output signal quality. The DDFS design has been modeled using register transfer level VHDL code and implemented on a field programmable gate array (FPGA). The design consumes 276 LUTs and 304 Flip-Flops on the FPGA and with dithering it is capable of reaching -72.5 dBc spurious free dynamic range (SFDR).