RTL Development Optimization by Reusing SystemC Model Testbench
Salman, Sarmad (2026)
2026
Master's Programme in Computing Sciences and Electrical Engineering
Informaatioteknologian ja viestinnän tiedekunta - Faculty of Information Technology and Communication Sciences
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Hyväksymispäivämäärä
2026-01-15
Julkaisun pysyvä osoite on
https://urn.fi/URN:NBN:fi:tuni-202601141453
https://urn.fi/URN:NBN:fi:tuni-202601141453
Tiivistelmä
Modern systems are growing increasingly complex, demanding equally sophisticated Systemon-Chip (SoC) solutions that require extensive design and verification effort. Verification alone accounts for the majority of the total development time and cost, largely due to the slow and resource-intensive nature of Hardware Description Language (HDL) based simulation. To address this challenge, this thesis explores a “shift-left” verification methodology aimed at enabling earlier validation and faster tape-out.
The proposed approach reuses existing SystemC transaction-level models (TLMs) to verify corresponding Register Transfer Level (RTL) implementations through a SystemVerilog Direct Programming Interface (DPI) interface. Unlike traditional co-simulation frameworks, the SystemC model and RTL remain decoupled, communicating only through shared memory provided by the operating system. This setup allows the high-level SystemC tests to execute independently and efficiently while the Unified Verification Methodology (UVM) environment acts solely as a passthrough interface, minimizing overhead.
By leveraging the speed and abstraction of SystemC, this methodology reduces dependency on licensed simulators, decreases engineering effort, and accelerates functional validation. This thesis aims to quantify the achievable verification coverage, measure reductions in verification effort, and assess the mutual consistency between SystemC models and RTL designs. The results demonstrate that SystemC-driven verification can achieve coverage comparable to traditional UVM for the evaluated tests, while reducing simulation cost and engineering workload. However, UVM remains necessary for timing-critical and corner-case verification, positioning the proposed flow as a complementary acceleration mechanism rather than a replacement. Through this, the proposed solution seeks to demonstrate a scalable and cost-effective verification framework for future SoC development.
For the evaluated test suite, the proposed SystemC-driven verification flow achieved functional coverage nearly identical to the UVM baseline, demonstrating that the decoupled co-simulation does not compromise verification quality. In addition, the methodology delivered a substantial performance improvement, reducing verification runtime and memory consumption by approximately 50%. These results highlight the practicality and efficiency of the approach, reinforcing its potential as a scalable acceleration mechanism for SoC verification.
The proposed approach reuses existing SystemC transaction-level models (TLMs) to verify corresponding Register Transfer Level (RTL) implementations through a SystemVerilog Direct Programming Interface (DPI) interface. Unlike traditional co-simulation frameworks, the SystemC model and RTL remain decoupled, communicating only through shared memory provided by the operating system. This setup allows the high-level SystemC tests to execute independently and efficiently while the Unified Verification Methodology (UVM) environment acts solely as a passthrough interface, minimizing overhead.
By leveraging the speed and abstraction of SystemC, this methodology reduces dependency on licensed simulators, decreases engineering effort, and accelerates functional validation. This thesis aims to quantify the achievable verification coverage, measure reductions in verification effort, and assess the mutual consistency between SystemC models and RTL designs. The results demonstrate that SystemC-driven verification can achieve coverage comparable to traditional UVM for the evaluated tests, while reducing simulation cost and engineering workload. However, UVM remains necessary for timing-critical and corner-case verification, positioning the proposed flow as a complementary acceleration mechanism rather than a replacement. Through this, the proposed solution seeks to demonstrate a scalable and cost-effective verification framework for future SoC development.
For the evaluated test suite, the proposed SystemC-driven verification flow achieved functional coverage nearly identical to the UVM baseline, demonstrating that the decoupled co-simulation does not compromise verification quality. In addition, the methodology delivered a substantial performance improvement, reducing verification runtime and memory consumption by approximately 50%. These results highlight the practicality and efficiency of the approach, reinforcing its potential as a scalable acceleration mechanism for SoC verification.