Hardware Implementation of a GRAND-AB(2) Decoder for BCH(79,64) Code
Sagir, Abdullah (2025)
2025
Tietotekniikan DI-ohjelma - Master's Programme in Information Technology
Informaatioteknologian ja viestinnän tiedekunta - Faculty of Information Technology and Communication Sciences
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Hyväksymispäivämäärä
2025-12-19
Julkaisun pysyvä osoite on
https://urn.fi/URN:NBN:fi:tuni-2025121811943
https://urn.fi/URN:NBN:fi:tuni-2025121811943
Tiivistelmä
Modern short block codes such as BCH codes remain attractive in embedded and low latency systems, but their conventional decoders (e.g., Berlekamp–Massey or Euclideanalgorithm based architectures) are tightly specialized to a given code and can be costly to redesign when the code changes. This thesis investigates a hardware implementation of a universal hard-decision decoding approach by targeting a GRAND-AB(2) (Guessing Random Additive Noise Decoding with abandonment 2) decoder for the BCH(79, 64) code.
The work develops a complete, reproducible design flow from algorithm to implementation. A bit accurate software reference model is created and used as a golden reference for functional verification. The decoder is implemented in SystemVerilog as a compact sequential architecture that stores the BCH parity check matrix as a column ROM and iteratively updates the syndrome while enumerating candidate noise patterns of Hamming weight 0, 1, and 2. Early termination is applied when a zero syndrome is reached, reducing average search effort. The design is verified using both directed tests (covering key control paths) and randomized batch tests against the golden model.
Finally, the implementation is synthesized and taken through an RTL to layout flow using an open source ASIC toolchain and a standard cell technology, and it is characterized in terms of post layout timing, area, and power, as well as decoder latency and throughput. The results demonstrate that GRAND-AB(2) can be realized as a practical hard decision decoder for BCH(79, 64), while preserving the key benefit of universality: supporting other linear block codes largely reduces to changing the parity check description rather than redesigning the core decoding datapath.
The work develops a complete, reproducible design flow from algorithm to implementation. A bit accurate software reference model is created and used as a golden reference for functional verification. The decoder is implemented in SystemVerilog as a compact sequential architecture that stores the BCH parity check matrix as a column ROM and iteratively updates the syndrome while enumerating candidate noise patterns of Hamming weight 0, 1, and 2. Early termination is applied when a zero syndrome is reached, reducing average search effort. The design is verified using both directed tests (covering key control paths) and randomized batch tests against the golden model.
Finally, the implementation is synthesized and taken through an RTL to layout flow using an open source ASIC toolchain and a standard cell technology, and it is characterized in terms of post layout timing, area, and power, as well as decoder latency and throughput. The results demonstrate that GRAND-AB(2) can be realized as a practical hard decision decoder for BCH(79, 64), while preserving the key benefit of universality: supporting other linear block codes largely reduces to changing the parity check description rather than redesigning the core decoding datapath.