FPGA-Based Prototyping and Performance Analysis of a Linux-Capable RISC-V SoC

Abstract

The growing complexity of modern Linux-capable System-on-Chip (SoC) designs makes early system-level validation increasingly important. FPGA-based prototyping provides a practical way to carry out such validation by enabling real hardware designs to run complete software stacks before tape-out. In parallel, the open and extensible RISC-V instruction set architecture has become widely adopted in both academia and industry. Despite this, to the best of our knowledge, only a limited number of published studies report the execution of full machine-learning frameworks directly on Linux-capable RISC-V soft cores implemented on FPGA. In this thesis, we present a complete and reproducible FPGA-based prototyping and performance evaluation flow for a Linux-capable open-source RISC-V SoC based on the Cheshire platform, implemented on the AMD-Xilinx Zynq UltraScale+ ZCU104 board. A full RISC-V Linux software stack comprising OpenSBI, U-Boot, and the Linux kernel is successfully integrated and brought up on the target platform. Moreover, native board support for the ZCU104 is developed as part of this work and contributed upstream to the official Cheshire repository. The system is evaluated using both a synthetic benchmark and a real application-level workload. When implemented as a single-core CVA6 system operating at 50 MHz, the platform achieves 1.98 CoreMark/MHz under bare-metal execution. In addition, a complete YOLOv8n object-detection pipeline is executed under Linux. End-to-end inference on a single image completes in approximately 45 minutes, with approximately 94% of the total execution time spent inside the ONNX Runtime inference call. All inference is performed on the general-purpose RISC-V core without hardware acceleration or framework-level optimizations. The obtained results provide a realistic performance baseline that can serve as a reference for future architectural exploration within the SoC Hub research environment.