Loss-Constrained Three-Level Optimized Pulse Patterns with Robustness to Power Factor Variations

Abstract

This paper presents the computation of three-level optimized pulse patterns (OPPs) that limit the converter losses while maintaining robustness against power factor variations. By constraining the switching and conduction losses of each semiconductor switch in the optimization process the trade-off between semiconductor losses and current harmonic distortions is improved. Moreover, to expand the solution space of the loss-constrained optimization problem, and thus increase the degrees of freedom in the optimization process, the symmetry properties of conventional OPPs are relaxed. Furthermore, to enhance the robustness of the proposed OPPs to changes in the power factor, the optimization problem constrains the semiconductor losses over a range of power factors rather than a single one, thereby reducing loss variation under different load conditions. As a result, the worst-case losses, and therefore the worst-case junction temperature, are reduced over a wide range of operating points, as shown with the presented numerical results.