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Customizing an Open-source RISC-V Microarchitecture for Real-time Performance

Kalache, Abdesattar (2025)

 
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Kalache, Abdesattar
2025

Tietotekniikan DI-ohjelma - Master's Programme in Information Technology
Informaatioteknologian ja viestinnän tiedekunta - Faculty of Information Technology and Communication Sciences
Hyväksymispäivämäärä
2025-04-22
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Julkaisun pysyvä osoite on
https://urn.fi/URN:NBN:fi:tuni-202504223893
Tiivistelmä
Real-time and mixed-criticality systems play a crucial role in safety-critical applications such as aerospace, automotive, and industrial automation. Traditionally, these systems relied on federated architectures with independent Electronic Control Units (ECUs). However, the shift toward integrated architectures has introduced new challenges in ensuring functional correctness, timing predictability, and efficient resource management. Although thread-based programming models are widely used in modern operating systems, their unpredictability, overhead, and complexity make them less suitable for real-time systems. In contrast, interrupt-driven programming models provide a more efficient alternative by enabling low-latency preemptive concurrency with minimal overhead.

This thesis addresses the limitations of existing real-time architectures by introducing RT-Ibex, an open-source RISC-V microarchitecture optimized for low-latency interrupt handling. RT-Ibex features a configurable interrupt interface with interrupt-level-based preemption and vectoring, significantly improving real-time responsiveness. To further enhance interrupt latency, we propose and evaluate hardware extensions, including ARM-style context switching and RISC-style register windowing, implemented in 22nm ASIC technology. Additionally, we introduce the Parallel Context Stack (PCS), a novel mechanism for ultra-fast context switching, and propose HETI, a heterogeneous interrupt architecture designed for area- and power-constrained platforms. Through integration and evaluation on an open-source RISC-V platform (Atalanta), RT-Ibex achieves a best-in-class 4-cycle interrupt latency while operating at 400 MHz. Performance analysis demonstrates significant improvements in execution efficiency and scalability compared to existing solutions, with HETI-2 and HETI-4 achieving 83% and 80% of instructions compared to the software baseline while maintaining an area overhead of less than 1.2%. These contributions establish RT-Ibex as a viable open-source alternative for real-time embedded applications, bridging the performance gap between RISC-V and proprietary architectures.
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  • Opinnäytteet - ylempi korkeakoulututkinto [40600]
Kalevantie 5
PL 617
33014 Tampereen yliopisto
oa[@]tuni.fi | Tietosuoja | Saavutettavuusseloste
 

 

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PL 617
33014 Tampereen yliopisto
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