Full-Duplexing with SDR Devices: Algorithms, FPGA Implementation and Real-Time Results

Abstract

In this paper, we present a novel nonlinear digital self-interference canceller algorithm, its implementation details on a software-defined radio (SDR) platform, and performance results of real-time full-duplex experiments on both device and link level. The canceller algorithm is based on an augmented Hammerstein model, with a nonlinear part modeling the transmitter non-idealities followed by a linear filter to model the self-interference (SI) channel. The nonlinear part includes a spline-based model for the nonlinear power amplifier, a polynomial model for baseband nonlinearities, as well as models for I/Q mismatch and LO leakage. The canceller is implemented on an FPGA as a part of an OFDM transceiver testbed for real-time measurements. Extensive real-time measurements show excellent performance: (1) the digital canceller, together with an RF isolator, can suppress the SI to within 1-2 dB’s of the receiver noise floor, with total SI suppression of up to 103 dB; (2) digital cancellation of up to 46 dB is evidenced, which is among the highest real-time cancellations in literature; (3) system-level measurements with OFDM signals demonstrate the benefit of utilizing the proposed canceller in a two-way communication scenario, showing up to 90% increase in sum-rate compared to half-duplex communication.