High-level synthesis of a long horizon model predictive control algorithm for an fpga

Khalid, Syed Ans Bin; Liegmann, Eyke; Karamanakos, Petros; Kennel, Ralph (2020)
 
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URI
https://ieeexplore.ieee.org/document/9178196


Khalid, Syed Ans Bin
Liegmann, Eyke
Karamanakos, Petros
Kennel, Ralph
2020

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https://urn.fi/URN:NBN:fi:tuni-202201101181

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Peer reviewed
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<p>This paper deals with a field-programmable gate array (FPGA) implementation of a long-horizon finite control set model predictive control (FCS-MPC) for a medium voltage drive system. By using the high level synthesis (HLS) tool from Xilinx, the VHDL code is directly generated from the C-code allowing for higher level of abstraction and faster prototype development. The controller execution time is under 20 μs during both steady-state and transient conditions, as confirmed by the presented results obtained based on a real-time “FPGA-in-the-loop” (FIL) implementation.</p>
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