Customized High Performance Low Power Processor for Binaural Speaker Localization

Behmann, N.; C. Seifert, C.; Paya-Vaya, G.; Blume, H.; Jääskeläinen, P.; Multanen, J.; Kultala, H.; Takala, J.; Thiemann, J.; van de Par, S. (2016)
 
Avaa tiedosto
Lataukset: 



Behmann, N.
C. Seifert, C.
Paya-Vaya, G.
Blume, H.
Jääskeläinen, P.
Multanen, J.
Kultala, H.
Takala, J.
Thiemann, J.
van de Par, S.
2016

This publication is copyrighted. You may download, display and print it for Your own personal use. Commercial use is prohibited.
doi:10.1109/ICECS.2016.7841215
Näytä kaikki kuvailutiedot
Julkaisun pysyvä osoite on
https://urn.fi/URN:NBN:fi:tuni-202010167360

Kuvaus

Peer reviewed
Tiivistelmä
This paper proposes a customized C programmable processor design to implement the propabilistic binaural speaker localization algorithm that fulfills the challenging requirements placed by the usage context. When compared to a VLIW-based processor design with similar basic computational resources and no special instructions, the proposed processor reaches a 151× speed-up. For a 28nm standard CMOS technology, power consumption of 12 mW (at 50 MHz) and silicon area of 0.3 mm2 is estimated. This is the first publication of a realistic programmable processing architecture for the probabilistic binaural speaker localization or a comparably complex algorithm for hearing aid devices.
Kokoelmat