Distributed SystemC Simulation on Manycore Servers

Abstract

SystemC (SC) is widely used in SoC simulations at various levels of abstraction. The free OSCI SC simulator can only execute on a single core in a sequential manner, which limits the simulation speed. Most speed-up techniques use threading, but this increases synchronization complexity and requires modifying the SC simulator kernel. We propose to use POSIX processes, and call it Inter Process Transaction Level Model (IPTLM) simulation. Our test case is a complete Kvazaar HEVC intra encoder. IPTLM offers 23x speed-up in a 28-core server compared with the standard monocore SC simulation time. IPTLM required manually modifying about 200 SC model code lines compared with the standard SC, which is reasonable when taking the achieved simulation speedup into account.