Three SoCs in three years - How to get agile?

Abstract

We taped out three large System-on-Chips in three years on 22nm CMOS technology, featuring multiple RISC-V cores, and subsystems for Machine Learning, Ethernet, Serdes, LP-DDR SDRAM, and IO. We have covered all steps in the flow from specification to sample chips. Ballast, Tackle, and Headsail include 130M, 12M, and 340M transistors and took 12, 10, and 9 calendar months. Several persons from seven companies and university contributed to the three chips and staff ranged from experts to novice master students. This paper provides insight into modern fast-paced System-on-Chip HW development which is important when Intellectual Properties such as RISC-V processors and security accelerators are evolving rapidly. We achieved agile development with the following guidelines: Intellectual Properties elaborated on the go, Staff moves along the design flow, Interface over instance, and Schedule over features. These are our reflections on the four Agile HW manifesto values to date.