Hardware Solutions for Eliminating Context Switching Latency in Processor-Based Hard Real-Time Systems

Abstract

Processor systems in control-oriented applications, such as safety-critical real-time systems, rely on low-latency context switching to service multiple tasks in a concurrent yet timely fashion. Conventional microcontroller systems rely on software-based storing and restoring of the active program context, while some microcontrollers have been optimized to accelerate the stacking of the context with custom hardware. However, these solutions do not address the fundamentally sequential nature of context saving. This publication presents a novel approach to parallelizing context saving and restoring by developing a parallel context stack. We integrate the solution into an existing open-source RISC-V processor and microcontroller platform and demonstrate the effective elimination of the context switch latency from the total interrupt latency. The design is synthesized with a commercial application-specific integrated circuit (ASIC) flow, using an open 45 nm technology library, and achieves a maximal frequency estimate of 500 MHz. The presented solution achieves a best-in-class total interrupt latency of 4 clock cycles, without increasing the critical path delay of the processor. We present a comparison of existing hardware mechanisms for context switching and an argument for improved safety and predictability with isolated context saving.