Towards Efficient OpenCL Pipe Specification for Hardware Accelerators

Abstract

FPGAs are programmable devices that are interesting for streaming-style applications. Using vendor-independent programming models such as OpenCL for FPGAs can aid the development effort and prevent vendor lock-in. OpenCL pipes included in the OpenCL standard offer a natural way to describe fine-grained task pipelines. However, the current use of the OpenCL pipe in FPGA OpenCL implementations is either non-compliant or not performance optimized due to several implementation challenges. In this paper we pinpoint the key implementation complexities and suggest possible specification updates and implementation choices that enable description of efficient task pipelines in a portable, vendor- and device-independent manner. We design a performance-optimized hardware pipe prototype, tackling a key challenge (runtime-defined connectivity) in going towards an OpenCL compliant, yet portable pipe implementation. The evaluation of our prototype on an FPGA shows that in a computer vision application, the proposed dynamically connected pipe component is 2.5x faster than an OpenCL buffer-based design. We evaluate the cost of the flexibility offered by the dynamic pipe prototype to be 4.4% in area utilization out of the total device resources and 1.6x latency overhead compared to a fixed connectivity design.