Generating CGRA Processing Element Hardware with CGRAgen

Abstract

The popularity of the Internet of Things and next-generation wireless networks calls for a greater distribution of small but high-performance and energy-efficient compute devices at the networks’ Edge. These devices must integrate hardware acceleration to meet the latency requirements of relevant use cases. Existing work has highlighted Coarse-Grained Reconfigurable Arrays (CGRAs) as suitable compute architectures for this purpose. However, like other modern hardware design, research and design space exploration into CGRAs is hindered by long development times needed for Register Transfer Level implementation. In this paper, we propose mitigating these by extending the open-source CGRAgen tool with a Chisel-based hardware backend capable of transforming abstract Processing Element (PE) descriptions into synthesizable Verilog code. We present how CGRAgen’s internal module representation is transformed to Chisel modules and demonstrate this on a selection of PE architectures from the literature. Finally, we outline future work on extending this flow to generate entire CGRAs.