Time synchronized co-simulation for pre-silicon SoC validation

Abstract

As the complexity of SoC (System-on-Chip) increases, there is a need for new novel design and testing techniques. One way the chip manufacturers aim to speed up the development process is by using comprehensive pre-silicon SoC validation. Pre-silicon SoC validation, also known as validation left-shifting is a process in which virtual platforms are used to test the integration of hardware and software components before the physical chip has been manufactured.

Virtual platforms enable the creation of co-simulation environments, in which simulators and emulators are used to concurrently model software and hardware components. An important as pect of a co-simulation environment is its ability to provide time synchronization between components so that the timing correctness and timing functionalities can be verified.

This thesis is written in commission to Nokia Solutions and Networks Oy, and it proposes a time synchronized co-simulation environment for pre-silicon SoC validation. The environment is built around Nokia’s in house developed TSS (Target SoC Simulator). TSS is a simulator for SoC simulation, verification, and validation and it provides mechanisms for connecting different types of models at different abstraction levels. TSS uses transaction objects to model register accesses between models. The environment includes QEMU (Quick Emulator) for processor and software modeling and a commercial logic simulator for RTL (Register Transfer Level) hardware modeling.

The environment utilizes internal time synchronization support of TSS. Instruction counting mechanism of QEMU is utilized to derive an estimate of elapsed time of machine instructions executed by a guest processor. QEMU models a guest processor by translating guest code to host code in so called translation blocks. After each translation block execution, elapsed time is calculated and passed to commercial simulator to advance its time accordingly. This procedure creates time synchronization between software and hardware models. Inter process communication methods such as named pipe and named semaphore are used to send timing information from QEMU to simulator.

The proposed co-simulation environment is evaluated in different co-simulation setups to obtain speed and accuracy metrics. It is observed that the accuracy of the co-simulation depends on the type of software that is executed on guest processor modelled by QEMU. This is due to the fact that translation blocks created by QEMU vary in length. According to measurements, the blocks tend to get longer when guest processor executes computationally intensive software. Longer translation blocks reduce the accuracy of the co-simulation, but it improves the speed because of less frequent need of communication between QEMU and simulator.

The communication delay between QEMU and commercial simulator is observed to be a major bottleneck that reduces the co-simulation performance. The large communication overhead stems from the usage of time consuming inter process communication methods. Another performance limiting factor is non-optimized transaction handling by RTL model, that continuously polls for upcoming transactions. The future work regarding the proposed co-simulation environment should focus on improving the communication infrastructure between QEMU and simulator and optimizing transaction handling on the RTL side.