CV-X-IF Based RISC-V Accelerator Generation

Abstract

The methods to enhance processor performance have expanded considerably in response to the increasing demand for modern computational tasks. Incorporating customized hardware acceleration with general-purpose processors can enhance speed and energy efficiency while preserving programmability. Processor microarchitecture-specific interface mechanisms for integrating them with the data path hinder the reusability with other processors. The Core-V eXtension Interface seeks to address this by establishing a standardized coprocessor interface for RISC-V processors. Furthermore, generating the hardware accelerators from an abstract description and integrating them via a standard interface reduces design effort.

This master’s thesis work developed a tool that generates customized RISC-V hardware accelerators that are compatible with Core-V eXtension by extending the OpenASIP tool set developed by the Customized parallel computing research group of the Tampere University. OpenASIP is an open-source tool set for customizing and generating hardware for application specific instruction set processors based on transport triggered architecture. However, it has the support for RISC-V as well. Furthermore, the tool set has retargetable compiler support. The implemented tool reuses the existing designing features of the OpenASIP and extend the hardware generation capabilities for the generation of hardware accelerators.

The special function units generated utilizing the tool were evaluated by implementing custom accelerated operations related to Fast Fourier Transformation algorithm and standard benchmarks while integrating with an existing RISC-V CPU. The generated FFT accelerator have shown an average execution time reduction of 34% compared to the execution on the general purpose processor. However, lack of the memory accessibility from the accelerator hinders the full potential.