Modular and Multicore RTIC: Multipass compilation, Distributions and Multicore support for hard real-time systems
Madaoui, Zakaria (2024)
2024
Tietotekniikan DI-ohjelma - Master's Programme in Information Technology
Informaatioteknologian ja viestinnän tiedekunta - Faculty of Information Technology and Communication Sciences
Hyväksymispäivämäärä
2024-12-05
Julkaisun pysyvä osoite on
https://urn.fi/URN:NBN:fi:tuni-2024120110654
https://urn.fi/URN:NBN:fi:tuni-2024120110654
Tiivistelmä
The Real-Time Interrupt-driven Concurrency (RTIC) framework is a powerful domain-specific language for developing reliable embedded systems. However, as it evolves to support increasingly complex features and compatibility across various hardware platforms and configurations, its monolithic and rigid codebase presents substantial challenges. This complexity makes the framework difficult to understand, maintain, and extend, which deters potential contributors and limits its adaptability.
This thesis focuses on enabling robust multicore support in RTIC. First, a modular architecture was introduced which leveraged Rust traits and a novel technique that involved multi-pass procedural macro expansions inspired by compiler multi-stage processing. This design reduced the framework's complexity and decoupled the core logic from hardware-specific dependencies. Furthermore, it provided the necessary foundation for integrating multicore support and new syntax features without overwhelming the codebase with additional complexity.
Extending the RTIC DSL to describe multicore systems posed further challenges and considerations which were thoroughly examined in this thesis. This includes the preservation of Stack Resource Policy (SRP) guarantees in the presence of cross-core shared resources, varying requirements between symmetric and asymmetric systems, and constraints such as single-binary and multi-binary outputs. The thesis also presents practical solutions to these problems and details their integration into the modular framework.
To validate the proposed approach, three reference implementations were developed: one for the RP2040 microcontroller, another for a simulated multicore ARM architecture using the Renode framework, and one targeting a single-core RISC-V soft-core implementation. These implementations demonstrate that the new architecture not only simplifies the integration of multicore functionality and new hardware targets but also lays the groundwork for future advancements in RTIC. By making the framework modular, flexible, and approachable, this work contributes to ensuring the continuation of RTIC's relevance as multicore architectures become more prevalent in embedded systems.
This thesis focuses on enabling robust multicore support in RTIC. First, a modular architecture was introduced which leveraged Rust traits and a novel technique that involved multi-pass procedural macro expansions inspired by compiler multi-stage processing. This design reduced the framework's complexity and decoupled the core logic from hardware-specific dependencies. Furthermore, it provided the necessary foundation for integrating multicore support and new syntax features without overwhelming the codebase with additional complexity.
Extending the RTIC DSL to describe multicore systems posed further challenges and considerations which were thoroughly examined in this thesis. This includes the preservation of Stack Resource Policy (SRP) guarantees in the presence of cross-core shared resources, varying requirements between symmetric and asymmetric systems, and constraints such as single-binary and multi-binary outputs. The thesis also presents practical solutions to these problems and details their integration into the modular framework.
To validate the proposed approach, three reference implementations were developed: one for the RP2040 microcontroller, another for a simulated multicore ARM architecture using the Renode framework, and one targeting a single-core RISC-V soft-core implementation. These implementations demonstrate that the new architecture not only simplifies the integration of multicore functionality and new hardware targets but also lays the groundwork for future advancements in RTIC. By making the framework modular, flexible, and approachable, this work contributes to ensuring the continuation of RTIC's relevance as multicore architectures become more prevalent in embedded systems.