Synthesis of Digital Quasi-Delay-Insensitive Greatest Common Divisor Circuit

Abstract

This work investigates the design of digital asynchronous quasi-delay-insensitive circuits with a focus on the methodology developed by Alain Martin [22]. While synchronous circuits have a global clock signal that drives the state machines forward, asynchronous counterparts use handshaking protocols. The lack of a global clock can offer multiple benefits, including lower power consumption, higher performance, plug-and-play modularity and reduced electromagnetic emissions. Even though multiple asynchronous processors and other circuits have been designed over the years, large-scale adoption by industry has been lacking due to lack of tools.

A high-level overview of quasi-delay-insensitive circuits and Martin's synthesis methodology is presented. The circuit is designed in multiple phases, starting from creating a specification via requirements gathering. Then the specification is implemented using a language called the Communicating Hardware Processes. A series of semantics preserving model transformations are executed until a CMOS netlist is obtained. Methodology is applied by synthesizing a greatest common divisor circuit by hand until a component netlist is obtained.