Verification of a heterogeneous multi-processor SoC

Abstract

System-on-chip (SoC) designs are getting more and more complex due to the constantly evolving semiconductor business. A single SoC can consist of a great number of sub-blocks such as CPUs, AI accelerators, memories, and interconnects. A heterogeneous structure enables the use of different kinds of processing units on the same chip. Resulting in greatly improved performance and power efficiency compared to homogeneous designs.

Verification is done to guarantee that a chip design is functional and ready for fabrication. More complex designs can be seen in verification as more time-consumed and as a need for more resources. The increasing complexity of the system greatly increases the number of configuration combinations which makes it a challenge for verification to cover all possible scenarios.

This thesis presents the verification process of Ballast SoC. Ballast is a heterogenous multi-processor SoC developed by SoC Hub. Firstly, the thesis studied SoCs and verification in general. In addition, related work was explored. Secondly, the thesis outlines the strategy and implementation for the Ballast verification process. The strategy section shows how the planning was done and what methods were used. The implementation section outlines the practical implementation of the verification. Finally, the results are presented.

The results presented in the thesis prove that the tapeout of Ballast SoC was reached with a high level of confidence. Later the Ballast samples arrived and the wake-up of the chip was started. Ballast was proven to be functional and only one major issue was found which affected only one of the nine subsystems.