Formal Verification based Security Verification in a System-On-Chip
Salminen, Niko (2023)
2023
Sähkötekniikan DI-ohjelma - Master's Programme in Electrical Engineering
Informaatioteknologian ja viestinnän tiedekunta - Faculty of Information Technology and Communication Sciences
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Hyväksymispäivämäärä
2023-05-29
Julkaisun pysyvä osoite on
https://urn.fi/URN:NBN:fi:tuni-202305226007
https://urn.fi/URN:NBN:fi:tuni-202305226007
Tiivistelmä
This thesis deals with formal verification based security verification in a System-on-Chip. First, the absolute basics of functional verification, such as simulation and emulation, are presented. Then, the basics of formal verification, such as the principles and limitations, are explained. Formal property verification is presented, together with the basic principles behind it.
Factors affecting the security of System-on-Chips are presented and how security can be enhanced through verification. The methods presented include examples of different SystemVerilog assertions that can be used to verify security.
In the practical part of this thesis, a flow for security verification for the top-level of a System-on Chip was implemented. The verification in the flow was performed by a formal verification tool. The results and suggestions for further research are presented at the end.
Factors affecting the security of System-on-Chips are presented and how security can be enhanced through verification. The methods presented include examples of different SystemVerilog assertions that can be used to verify security.
In the practical part of this thesis, a flow for security verification for the top-level of a System-on Chip was implemented. The verification in the flow was performed by a formal verification tool. The results and suggestions for further research are presented at the end.