Bringing up RISC-V Interrupts using Rust Programming Language

Abstract

RISC-V ISA is a popular open and royalty-free ISA that enables the development of low-cost Systems-on-Chip (SoCs). Ballast is a novel multicore RISC-V-based SoC developed by SoC Hub in collaboration with different companies for Internet of Things (IoT) applications. It includes multiple subsystems that feature three RISC-V cores. Interrupts allow processor power saving and fast interaction with external pe- ripherals. Having proper software support for interrupts enables easy and accurate configuration. Additionally, safety is a concern, and having a language that guar- antees safe operation, such as Rust, will minimize catastrophic bugs. This thesis outlines the process of implementing interrupt software support in the Ballast SoC using the Rust programming language, as well as test techniques for ensuring proper interrupts operation. Software support was implemented as part of Hardware Abstraction Layer (HAL), and two use cases were developed to test the implemented software and validate interrupts on the Ballast SoC development board. Interrupts were successfully brought up in Ballast SoC and were proven to func- tion correctly using the test methodologies introduced in this thesis. Moreover, the developed software support can easily be utilized on other SoCs that use similar cores (such as the new SoC Hub chip Headsail) by including it as a dependency crate using Cargo tool.