BootROM Development for a Novel Multiprocessor System-on-Chip
Nurmi, Antti (2022)
2022
Sähkötekniikan DI-ohjelma - Master's Programme in Electrical Engineering
Informaatioteknologian ja viestinnän tiedekunta - Faculty of Information Technology and Communication Sciences
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Hyväksymispäivämäärä
2022-02-24
Julkaisun pysyvä osoite on
https://urn.fi/URN:NBN:fi:tuni-202112179320
https://urn.fi/URN:NBN:fi:tuni-202112179320
Tiivistelmä
Heterogeneous multiprocessor system-on-chips are the favorable platform for embedded systems with tight requirements for both energy efficiency and performance. The Ballast system-on-chip is a novel heterogeneous multiprocessor system-on-chip platform developed at Tampere University in co-operation with several companies and features three processor subsystems, a digital signal co-processor subsystem and an artificial intelligence accelerator subsystem.
The boot process of commercial processor platforms is typically hidden from the end user. In this thesis the boot process for Ballast is developed from scratch with the target of providing multiple reliable boot alternatives for this specific system while researching generally applicable principles of boot process development. The redundancy brought by multiple boot alternatives was chosen as the main method of providing reliability to the boot process. Four distinct boot modes were conceived for the system: the SDIO mode, SPI mode, external mode and JTAG mode. The alternatives implement the same core functionality of loading a software image to on-chip memory, except for the external boot, which is based on executing the image directly from an external memory.
Software development methodologies were studied to develop the first level of boot software that will be fabricated to a read-only memory on the system. The effects of programming language selection, runtime initialization, optimization and linking are explored. The synthesis of a hardware description language module based on an executable software image is also addressed.
The verification of hardware designs can be performed with simulation and prototyping. The simulation of hardware can be performed on four abstraction levels: the transistor level, the gate level, the register transfer level and the processor level. In prototyping, the design is emulated on a programmable hardware platform, typically a field programmable gate array.
The final boot code was compiled from four source files and was implemented on a hardware module with a size of 3 kB. The functionality of the boot process in all four boot modes was verified with the transfer and execution of multiple test software images. The verification of the boot process was performed mainly in register transfer level simulation and field programmable gate array based prototyping. The proposed boot process with it’s alternative operating modes was implemented and verified successfully with all tested scenarios.
The boot process of commercial processor platforms is typically hidden from the end user. In this thesis the boot process for Ballast is developed from scratch with the target of providing multiple reliable boot alternatives for this specific system while researching generally applicable principles of boot process development. The redundancy brought by multiple boot alternatives was chosen as the main method of providing reliability to the boot process. Four distinct boot modes were conceived for the system: the SDIO mode, SPI mode, external mode and JTAG mode. The alternatives implement the same core functionality of loading a software image to on-chip memory, except for the external boot, which is based on executing the image directly from an external memory.
Software development methodologies were studied to develop the first level of boot software that will be fabricated to a read-only memory on the system. The effects of programming language selection, runtime initialization, optimization and linking are explored. The synthesis of a hardware description language module based on an executable software image is also addressed.
The verification of hardware designs can be performed with simulation and prototyping. The simulation of hardware can be performed on four abstraction levels: the transistor level, the gate level, the register transfer level and the processor level. In prototyping, the design is emulated on a programmable hardware platform, typically a field programmable gate array.
The final boot code was compiled from four source files and was implemented on a hardware module with a size of 3 kB. The functionality of the boot process in all four boot modes was verified with the transfer and execution of multiple test software images. The verification of the boot process was performed mainly in register transfer level simulation and field programmable gate array based prototyping. The proposed boot process with it’s alternative operating modes was implemented and verified successfully with all tested scenarios.