Fast Fourier Transform Power Consumption Optimization
Paananen, Teemu (2021)
2021
Tietotekniikan DI-ohjelma - Master's Programme in Information Technology
Informaatioteknologian ja viestinnän tiedekunta - Faculty of Information Technology and Communication Sciences
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Hyväksymispäivämäärä
2021-05-05
Julkaisun pysyvä osoite on
https://urn.fi/URN:NBN:fi:tuni-202104284029
https://urn.fi/URN:NBN:fi:tuni-202104284029
Tiivistelmä
Fast Fourier Transform (FFT) is a signal processing algorithm used to obtain spectral content of a time domain data sequence. It is a computationally intensive algorithm, so it can form a substantial part of the power consumption of the system it is used in. Therefore, optimizing the FFT can bring cost savings in power supply and cooling of the system.
In this thesis, an existing FFT design is optimized to reduce its power consumption. The optimization is done on Register-Transfer Level (RTL) using VHDL. The theoretical background of the topic is first covered, presenting various ways the FFT can be implemented and how the power consumption can be reduced. This information is then taken into the implementation, where the original design is optimized by updating it to use a more efficient FFT algorithm. The algorithm used in the original design was radix-22, which can be optimized by reducing the number of complex multiplications in it. To do this, the radix-23 algorithm was implemented. It decomposes and combines the complex multiplications, so that part of the operations can be done by using simpler multiplication logic.
The RTL implementation of the design is described, showing what updates were done to the original design. The two are then simulated for average power consumption, using all supported transform sizes and numbers of parallel samples. The results are compared to determine the gained savings and the new design is found to reduce the power consumption by 10% at best. This is achieved with an 8192-point transform and 8 parallel samples, which are the maximum the design supports.
In this thesis, an existing FFT design is optimized to reduce its power consumption. The optimization is done on Register-Transfer Level (RTL) using VHDL. The theoretical background of the topic is first covered, presenting various ways the FFT can be implemented and how the power consumption can be reduced. This information is then taken into the implementation, where the original design is optimized by updating it to use a more efficient FFT algorithm. The algorithm used in the original design was radix-22, which can be optimized by reducing the number of complex multiplications in it. To do this, the radix-23 algorithm was implemented. It decomposes and combines the complex multiplications, so that part of the operations can be done by using simpler multiplication logic.
The RTL implementation of the design is described, showing what updates were done to the original design. The two are then simulated for average power consumption, using all supported transform sizes and numbers of parallel samples. The results are compared to determine the gained savings and the new design is found to reduce the power consumption by 10% at best. This is achieved with an 8192-point transform and 8 parallel samples, which are the maximum the design supports.