Configurable Runtime On-chip FPGA Logic Debugging and Its Challenges
Shariat Nasseri, Mohamad Ibrahim (2021)
2021
Master's Programme in Information Technology
Informaatioteknologian ja viestinnän tiedekunta - Faculty of Information Technology and Communication Sciences
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Hyväksymispäivämäärä
2021-04-28
Julkaisun pysyvä osoite on
https://urn.fi/URN:NBN:fi:tuni-202104263681
https://urn.fi/URN:NBN:fi:tuni-202104263681
Tiivistelmä
There are many solutions to debug an FPGA design. Some are industry standards, and some are custom-made for specific cases and projects. In the context of on-chip debugging, there are solutions such as using external measurement tools, direct instrumentation (or modification) of the bitfiles, commercial embedded logic analysers or custom embedded logic analysers using trace buffers. Although these approaches utilize the speed of on-chip testing, they either lack visibility or they take up too much of the FPGA resources to be Implemented. To simplify comparison between different methods, four design criteria are defined: visibility, flexibility, logic overhead and debugging cycle.
In this thesis, an alternative approach for on-chip debugging is provided that can utilize the speed of running on the chip, while it uses minimal amount of the FPGA resources. The approach is in a form of an intellectual property (IP) called snapshot IP. It has two functionalities, capture and insertion. Capture functionality can sniff the ongoing data between two IPs and offloaded to a memory space for an offline check, while insertion can inject data to an IP for validation purposes. There are multiple modes of operation in both capture and insertion to choose from depending on testing scenarios. Snapshot IP provides a set of features to enhance flexibility of debugging process. Examples of such features are timing-based or pattern-based capture, support for multiple data formats and two simultaneous memory access. Also, the IP has multiple clock inputs for the cases where stream and memory sides are operating on different clock frequencies. User has control over the start and stopping of the operations and can define the memory area to be used.
Moreover, in implementation chapter, the design decisions, challenges, and limitations of such design as a high-performance debugging solution are discussed. Challenges are categorized into three sections: design, design flow and validation challenges. Limitations are the inability to insert any arbitrary data, performance sensitivity on external factors and the fact that the design is only a complimentary solution to other debugging and validation methods. The FPGA in use is Intel Stratix 10 SX.
In terms of results, the final design has met the target that is aimed for. When implemented, each instance of Snapshot IP roughly takes 0.3-0.4% of logic on the FPGA and 0.5% of available M20K memory blocks, showing low level of logic overhead. The Ip can handle ~16 Gbps data on its AXI4 interface toward memory. Throughout the design process, there were bugs such as AXI4 bus jamming that were fixed in the final design. Also, preparing for a new round of debugging is simple, visibility is on an acceptable level. Finally, the feature set helps to have decent flexibility.
In this thesis, an alternative approach for on-chip debugging is provided that can utilize the speed of running on the chip, while it uses minimal amount of the FPGA resources. The approach is in a form of an intellectual property (IP) called snapshot IP. It has two functionalities, capture and insertion. Capture functionality can sniff the ongoing data between two IPs and offloaded to a memory space for an offline check, while insertion can inject data to an IP for validation purposes. There are multiple modes of operation in both capture and insertion to choose from depending on testing scenarios. Snapshot IP provides a set of features to enhance flexibility of debugging process. Examples of such features are timing-based or pattern-based capture, support for multiple data formats and two simultaneous memory access. Also, the IP has multiple clock inputs for the cases where stream and memory sides are operating on different clock frequencies. User has control over the start and stopping of the operations and can define the memory area to be used.
Moreover, in implementation chapter, the design decisions, challenges, and limitations of such design as a high-performance debugging solution are discussed. Challenges are categorized into three sections: design, design flow and validation challenges. Limitations are the inability to insert any arbitrary data, performance sensitivity on external factors and the fact that the design is only a complimentary solution to other debugging and validation methods. The FPGA in use is Intel Stratix 10 SX.
In terms of results, the final design has met the target that is aimed for. When implemented, each instance of Snapshot IP roughly takes 0.3-0.4% of logic on the FPGA and 0.5% of available M20K memory blocks, showing low level of logic overhead. The Ip can handle ~16 Gbps data on its AXI4 interface toward memory. Throughout the design process, there were bugs such as AXI4 bus jamming that were fixed in the final design. Also, preparing for a new round of debugging is simple, visibility is on an acceptable level. Finally, the feature set helps to have decent flexibility.