Merge and Prune Based Automated Generation of Co-Processor Architectures
Hirvonen, Alex (2021)
2021
Sähkötekniikan DI-ohjelma - Master's Programme in Electrical Engineering
Informaatioteknologian ja viestinnän tiedekunta - Faculty of Information Technology and Communication Sciences
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Hyväksymispäivämäärä
2021-04-29
Julkaisun pysyvä osoite on
https://urn.fi/URN:NBN:fi:tuni-202104263563
https://urn.fi/URN:NBN:fi:tuni-202104263563
Tiivistelmä
Modern digital systems can be described as multiprocessor system on chip (MPSoC). Multiple customized processors orchestrated by the master processor that offloads some specific tasks to them. Application-specific instruction set processors (ASIP) or co-processors offer high performance and efficient power usage in a small size over traditional general-purpose processors (GPP). They are also flexible to customize and extend for future updates, but their development can be complex, time-consuming, and costly.
TTA-Based Co-Design Environment (TCE) framework offers a toolchain to develop customized processors using Transport Trigger Architecture (TTA). It provides the required tools to design and evaluate processors using customized processor template. The modularity and flexibility of TTAs offer a multitude of different ways to customize a processor using designer parameters but introduces large design space, which is impossible to explore without proper design automation heuristics. Also, some of the processor design steps are manual, which is slow and error-prone.
For this thesis, an advanced heuristics to explore and prune large TTA processor design space is introduced. The heuristics find suitable processor architectures based on the designer input parameters. Besides, an automated design flow is created to speed up the design process and minimize error risks. The design is fully automated starting from an application written in the-high level language and produces hardware description language code, suitable to run on field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC).
TTA-Based Co-Design Environment (TCE) framework offers a toolchain to develop customized processors using Transport Trigger Architecture (TTA). It provides the required tools to design and evaluate processors using customized processor template. The modularity and flexibility of TTAs offer a multitude of different ways to customize a processor using designer parameters but introduces large design space, which is impossible to explore without proper design automation heuristics. Also, some of the processor design steps are manual, which is slow and error-prone.
For this thesis, an advanced heuristics to explore and prune large TTA processor design space is introduced. The heuristics find suitable processor architectures based on the designer input parameters. Besides, an automated design flow is created to speed up the design process and minimize error risks. The design is fully automated starting from an application written in the-high level language and produces hardware description language code, suitable to run on field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC).