Automated register generation from IP-XACT : Generating VHDL file from IP-XACT formatted XML using Python3 and its’ libraries

Abstract

The System on Chip (SoC) field relies on tools and processes. Tools are used for design, automation and verification purposes. Automation tools do repetitive tasks and one of these tasks would be generation of register banks. Register banks are fast memory of SoC modules and each SoC module requires their own set of registers to suit module’s needs. Register bank generation tools enable developers to quickly generate registers for a SoC module according to a register configuration file. In this thesis project there is an existing register generator tool flow that uses IP-XACT as intermediate file format. This IP-XACT file is interpreted and VHDL is generated based on its’ data. The previously developed tool that does the conversion has become very fragile to changes and its’ programming language differs from the rest of the flow. This thesis describes the update to the IP-XACT to VHDL flow. A database is planned to be used as an intermediate format between IP-XACT and VHDL. A database approach would enable easy modifications, big and small, and the database is constructed in such a way that IP-XACT can be regenerated from it. Tool was developed for the flow and is available alongside the old implementation. The development was successful since the tool is able to transfer the information from IP-XACT file to database losslessly and then generate a VHDL file according to a register description from the IP-XACT file stored in the database. The tool has gone through verification and continues to be in development for extended functionality. Otherwise, the tool is in support mode and provides its’ intermediate database for other flows.