Operation set customization in retargetable compilers
Kultala, Heikki; Jääskeläinen, Pekka; Takala, Jarmo (2011)
Lataukset:
Kultala, Heikki
Jääskeläinen, Pekka
Takala, Jarmo
IEEE Computer Society
2011
Julkaisun pysyvä osoite on
https://urn.fi/URN:NBN:fi:tty-201205211142
https://urn.fi/URN:NBN:fi:tty-201205211142
Kuvaus
Peer reviewed
Tiivistelmä
The core tool in Application-Specific Instruction Set Processor (ASIP) design toolsets is a retargetable compiler, which can generate efficient code to any processor developed with the toolset. Such a compiler must automatically adapt itself to the operation set supported by the designed processor by emulating missing instructions with other instructions and by selecting custom instructions automatically whenever possible. This paper proposes a simplified Directed Acyclic Graph-based recursive mechanism to support operation set customization. The proposed mechanism is capable of generating instruction selectors and architecture simulation models automatically, thus is suitable for fast design space exploration of ASIP operation sets.
Kokoelmat
- TUNICRIS-julkaisut [19020]